1. Field of the Invention
This invention relates to integrated circuits and more particularly relates to an apparatus and method of fabricating an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance and facilitates increased surface area coupling between the interlevel interconnect and source/drain region(s).
2. Description of the Related Art
A typical integrated circuit includes a large number of circuit devices such as insulated gate field effect transistors (IGFETs) and other circuit devices which are fabricated on a single substrate, normally silicon. The functionality of the integrated circuit depends in part on interconnections between various circuit devices. As integrated circuits increased in size and complexity, multilevel interconnect structures were introduced to address the massive interconnection requirements. For example, multilevel interconnect structures have been extensively utilized in conjunction with complimentary metal oxide semiconductor (CMOS) technology, bipolar technology, and a combination of bipolar and CMOS ("BiCMOS") technologies to obtain interconnection flexibility and size reductions considered advantageous in the current integrated circuits marketplace.
Referring to FIG. 1a, fabrication of the multilevel interconnect structure of integrated circuit 100 is preceded by the fabrication of an exemplary N-channel IGFET 101. IGFET 101 includes field oxide isolation regions 120 and 122 which are formed in substrate 110 to isolate the IGFET 101 from adjacent devices (not shown). The IGFET 101 of conventional integrated circuit 100 uses a polysilicon gate 102, separated from the substrate 110 by a thin insulating layer 112, to control an underlying surface region 104 which joins doped source/drain 106 and source/drain 108. The source/drain 106 and source/drain 108 are doped oppositely to the channel 104 and the substrate 110. The operation of the IGFET 101 involves application of an input voltage to the gate 102, which sets up a transverse electric field in the channel 104 to modulate the conductance of the channel 104 between source/drain 106 and source/drain 108.
Referring to FIGS. 1a and 1b, following fabrication of the IGFET 101, an insulation layer 114, such as chemical vapor deposition (CVD) silicon dioxide, is conformally formed over the IGFET 101 and substrate 110. Contact holes (also referred to as `windows`) are then typically opened through the insulation layer prior to formation of the overlying thin film interconnects 116 and 118 and filled with a conductive film to form contacts 103[a:h] i.e. contacts 103a through 103h. IGFET 101 is interconnected with other circuit devices (not shown), generally using patterned high conductivity, thin film structures, such as metal interconnects 116 and 118. Metal interconnects are patterned above insulation layer 114. Contacts 103[a:h] electrically connect interconnects 116 and 118 with source/drain 106 and source/drain 108, respectively. Multiple contacts 103[a:h] are formed between interconnects 116 and 118 and source/drain 106 and source/drain 108, respectively, in an attempt to maximize the contact area with source/drain 106 and source/drain 108 and thus reduce resistance and current density of contacts 103[a:h].
Referring to FIGS. 1a, 1b, and 2, contacts 103[a:h] interface with only a relatively small proportion of available source/drain 106 and 108 surface area. Source/drains 106 and 108 are oversized to accommodate the full range of misalignment errors associated with various fabrication tolerances such as lithography and mask registration tolerances. It is undesirable to misalign contacts 103[a:h] such that one or more of the windows for contacts 103[a:h] encroach beyond the outer perimeter of the source/drain regions 106 and 108. This is particularly the case when insulation layer 114 is generally aggressively etched to open a contact hole. FIG. 2 illustrates an overetched, misaligned contact hole with contact 202 being misaligned in a direction towards isolation field oxide 204, a portion of the contact 202 extends into isolation field oxide 204 below source/drain 205 and contacts substrate 206 below source/drain regions 106 and 108. Contact 202 represents a misaligned one of contacts 103[a-h]. The misalignment and degree of overetching cause several problems including excessive leakage current at the contact 202 to substrate 206 at intersection 208. Also, misalignment of contacts 103[a:h] in the direction of gate 102 will cause an electrical short between gate 102 and a contact(s) if the contacts 103[a:h] impinge upon gate 102. Thus, especially as dimensions of the IGFET 101 approach 1 .mu.m and below, the area of the source/drain regions 106 and 108 are not minimized to present a contact surface matching the contacting surface dimensions of contacts 103[a:h] so that the source/drain regions 106 and 108 provide adequate tolerance for misalignment of contacts 103[a:h]. Once misalignment errors are characterized, contacts 103[a:h] are usually uniformly sized to provide a known contact area between contacts 103[a:h] and source/drain regions 106 and 108 without encroaching into isolation regions 120 and 122. Typically, contacts 103[a:h] contact about 20 percent of the surface area of source/drains 106 and 108.
In the event that the misaligned contact hole does not completely extend below source/drain 205, even the minimum degree of overetching to near the underside of source/drain 205 disadvantageously increases the parasitic capacitance between contact 202 and substrate 206.
To prevent misalignment errors, extra surface area for source/drain regions 106 and 108 is thus allocated to accommodate misalignment of contacts 103[a:h]. However, the larger source/drain regions 106 and 108 areas result in increased source/drain 106 to substrate 110 and source/drain 108 to substrate 110 parasitic capacitance. This increased capacitance reduces the speed performance of the IGFET 101. Additionally, the oversized source/drain regions 106 and 108 decrease the device packing density of integrated circuit 100. For more information regarding exemplary conventional contact technology, please refer to Wolf, Silicon Processing for the VLSI Era--Volume II, Lattice Press pub., chapter 3, including page 143, which is incorporated herein by reference.
Referring to FIG. 3, integrated circuit 300 includes IGFET 302 having impurity doped source/drain regions 304 and 306 on substrate 308. Isolated polysilicon runners 310 and 312 are patterned in field regions 314 and 316, respectively, concurrently with polysilicon gate 318. Following formation of the lightly doped source/drain regions 320 and 322 and source/drain 304 and 306, a thin layer of chemical vapor deposited tungsten is selectively deposited onto the polysilicon gate 318, the exposed source/drain regions 304 and 306, and the isolated polysilicon runners 310 and 312 to form local interconnects 324 and 326. The local interconnects 324 and 326 generally provide electrode interconnections between adjacent active devices and are consequently formed under dielectric layer 328. Thus, following formation of local interconnects 324 and 326, a dielectric layer 328 is deposited over IGFET 302 and local interconnects 324 and 326. However, additional process steps are required to open contact windows through dielectric layer 328 and fill the contact windows with a conductor to form contacts 330 and 332 to connect local interconnects to the next interconnect level.
Additionally, potentially difficult masking, etching, and mask removal steps are required to remove polysilicon spacers 334 and 336 (shown with dotted lines) formed with polysilicon runners 310 and 312.
Accordingly, a need exists for reducing contact to substrate parasitic capacitance and short circuits when a contact extends over a source/drain region boundary. Furthermore, a need exists for smaller source/drain regions 106 and 108. Additionally, a need exists for a flexible interconnect structure fabricated using an efficient process.